The present application relates to systems, devices and methods for maskless material deposition on substrates using charged particle beams; and more particularly to directly depositing material at precise locations as defined in a design layout database using multiple, matched charged particle beams, with the assistance of gas and/or photon injection, and/or of gas and/or photon process control, metrology and endpoint detection.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
FIG. 2A shows an example of a wafer 200 being scanned by multiple charged particle beams 204 emitted by respective miniature electrostatically-deflected beam columns 206. Individual columns 206 are able to target a portion 202 of the substrate surface with their respectively emitted beams 204.
FIG. 2B shows an example of a wafer 200. Example die 208 size and column 206 center-to-center spacing 210 (column separation) are shown. A regular grid of columns 206 (columns 206 are shown via their center positions, represented here as plusses) can use different spacing 210 in different (generally, orthogonal) directions. Die 208 size and column separation 210 are not required to (and generally, will not) correspond. Column separation 210 generally corresponds to the “writing area” of corresponding columns 206. A column's 206 “writing area” is defined as the substrate area 202 targetable by a charged particle beam 204 emitted from the column 206, taking into account stage movement.
The multiple column 206 array comprises miniature (small enough to fit multiple columns in an array) charged particle beam columns 206 arranged in a regular grid. For example, column 206 arrays with center-to-center column spacing 210 of 30 mm×30 mm have been implemented, though other column spacings 210 (e.g., 24 mm×33 mm) can also be used.
A stripe is the portion of the wafer 200 surface that a charged particle beam can target while the stage is moving predominantly in a single direction, i.e., before the stage moves laterally and switches predominant directions to give the beam access to a different stripe. A “frame” is defined herein as the portion of the wafer surface that a beam can target at a given time, corresponding to the main-field deflection area at that time, as designated by the design layout database. A frame is typically designated to be rectangular, for convenience (e.g., to tile the writing area); and smaller than the furthest extent to which the beam can be deflected (e.g., to preserve beam targeting accuracy).
“1-D” refers to 1-D gridded design rule. In a 1-D layout, optical pattern design is restricted to lines running in a single direction, with features perpendicular to the 1-D optical design formed in a complementary lithography step known as “cutting”. The complementary step can be performed using a charged particle beam lithography tool comprising an array of columns 206—for example, electrostatically-controlled miniature electron beam columns 206. A 1-D layout is separated in the design layout database into a “line pattern” and a “cut pattern”. The design layout database contains the information needed by lithography tools to pattern one or more layers on a substrate. A line pattern generally comprises an array of unidirectional lines. Cut patterns generally comprise line-cuts and holes.
Generally, line patterns are written by an optical lithography system, which can be followed by other process steps to increase the density of lines on the substrate. Cut patterns are written by a complementary (generally higher-resolution) process, such as electron beam lithography. Use of electron beam lithography for this complementary process is also called complementary e-beam lithography, or CEBL. The combination of the line-forming process followed by line-cuts written with CEBL to pattern a substrate layer is called complementary lithography.
FIG. 2C shows an example of a prior art process for depositing material onto a substrate surface.
Typically, as shown in FIG. 2C, a design layout database is used to designate where on a substrate material should be deposited 212 (e.g., to form new pattern or repair previously-formed pattern). One or more optical masks are fabricated based on the design layout database 214 using a mask making tool 216. Fabrication of an optical mask typically takes weeks and costs millions of dollars at advanced process nodes.
A pattern material (a material in which it is desired to express the pattern designated by the design layout database, e.g., a functional or structural material) is blanket deposited 218 and a hard mask is blanket deposited 220 on the substrate surface by a deposition tool 222. A photoresist layer is blanket deposited on the substrate surface 224 by a resist deposition tool 226.
“Blanket” deposition and etch generally refers to deposition and etch on the entire surface of the substrate.
“Resist” refers herein to a class of materials used in substrate lithography. When a resist is deposited on a substrate and exposed to an energy source corresponding to the type of resist (e.g., photons for a photoresist) in a chosen pattern, its chemical properties change such that when the resist is developed (in ways similar to developing a photographic film), a portion of the resist corresponding to a positive or negative image of the pattern (depending on the type of resist) will remain, allowing the pattern to be expressed in the material underlying the resist, e.g., using etch steps.
The photoresist is then exposed using the optical mask(s) 228 by an optical lithography tool 230. The exposed portion of the substrate (as designated by the optical mask(s)) is removed 232 using a resist developing tool 234, and the resulting patterned resist layer is inspected for defects and process control metrology (After Develop Inspection (ADI) and metrology) 236 by an inspection tool 238.
The hard mask is then blanket etched through the pattern expressed in the resist layer 240 by an etch tool 242 to express (substantially) the same pattern in the hard mask layer. The resist layer is then removed 244 by a resist removal tool 246, and the material underlying the hard mask is blanket etched through the pattern expressed in the hard mask 248, using an etch tool 250 (e.g., a reactive-ion etch or ion milling tool, generally the same type of tool as etch tool 242), to express (substantially) the same pattern in the underlying (pattern) material (newly added in step 220). The hard mask is then removed 252 using a hard mask removal tool 254. One of ordinary skill in the arts of charged particle beam material deposition will understand that other and/or additional steps can be used in a conventional material deposition process.
Ti represents the amount of time added by a corresponding process step. Yi represents the yield impact of a corresponding process step (one minus probability of introducing one or more yield-reducing defects). Where T is the total time taken by a material deposition process, and Y is the expected yield following a material deposition process:T=Σi=1NTi  Equation 1:Y=Πi=1NYi  Equation 2:
Numerous steps in conventional semiconductor lithography material deposition processes are expensive and time consuming, and potentially introduce defects into the desired pattern, lowering yield. Process-induced defects can be introduced by, for example, wafer handling, resist spin and heating, lithography, resist development, etch, deposition, inspection, implantation, thermal processing, and chemical-mechanical polishing.